1. Field of the Invention
The present invention relates to a semiconductor wafer surface flattening apparatus for flattening the surfaces of semiconductor wafers by chemical-mechanically polishing the surfaces of the semiconductor wafers using polishing pads and a polishing liquid.
2. Description of Related Art
For example, a conventional semiconductor wafer surface flattening apparatus of this type has been disclosed in a European patent application on May 21, 1997, (Disclosure Number: EPO774323A2, Title of the Invention: APPARATUS AND METHOD FOR POLISHING SUBSTRATES). This apparatus is generally called a CMP (Chemical Mechanical Polish) apparatus. FIG. 1 shows an oblique view of the structure of this apparatus.
Three rotating surface plates (platens) 2, 3, and 4, and a load-and-unload station 5 are installed on a base 1. A polish pad is glued on the surface of each of the platens 2, 3, and 4. Dressers 6, 7, and 8 for polishing the surfaces of these polishing pads are installed near the platens 2, 3, and 4, respectively. A freely rotatable carousel 9 is installed on the base 1. The carousel 9 supports four carriers 10, 11, 12, and 13. Each of the four carriers 10, 11, 12, and 13 holds a semiconductor wafer. When the carousel 9 rotates by a prescribed angle, the carousel 9 indicates the rotation positions of the semiconductor wafers the carriers 10 through 13 are holding.
In an operation mode, called the in-line mode, the three platens 2, 3, and 4 separately and sequentially polish the surfaces of multiple semiconductor wafers for the first time. For example, this polish operation is carried out in the following manner.
First, a robot not shown in FIG. 1 loads a first semiconductor wafer W from a wafer cassette onto the load-and-unload station 5. As shown in FIG. 2A, the carrier 10 holds this first semiconductor wafer W. Next, as shown in FIG. 2B, the carousel 9 rotates counterclockwise by 90 degrees, and transports the first semiconductor wafer W onto the platen 2. Then, as the carrier 10 presses with a prescribed pressure the first semiconductor wafer W onto the polish pad that is installed on the platen 2, a polish liquid (slurry) is supplied to the polish pad. Then as the platen 2 and the carrier 10 rotate, the first semiconductor wafer W is chemical-mechanically polished for a minute. While the first semiconductor wafer W is being polished, a second semiconductor wafer W is loaded onto the load-and-unload station 5. The carrier 11 then picks up and holds the loaded second semiconductor wafer W.
When the platen 2 finishes polishing the first semiconductor wafer W for the first time, the carousel 9 rotates counterclockwise by 90 degrees. Subsequently, as shown in FIG. 2C, the carrier 10 moves onto the platen 3 and the carrier 11 moves onto the platen 2. Then the platen 3 chemical-mechanically polishes the first semiconductor wafer W for the second time for a minute. At the same time, the platen 2 chemical-mechanically polishes the second semiconductor wafer W for the first time for a minute. During this one minute, a third semiconductor wafer W is loaded onto the load-and-unload station 5. Then the carrier 12 picks up and holds the loaded third semiconductor wafer W.
Next, the carousel 9 rotates counterclockwise by 90 degrees. Consequently, as shown in FIG. 2D, the carrier 10 is moved onto the platen 4, the carrier 11 is moved onto the platen 3, and the carrier 12 is moved onto the platen 2. Then the platen 4 chemical-mechanically polishes the first semiconductor wafer W for the third and last time for a minute. At the same time, the platen 3 chemical-mechanically polishes the second semiconductor wafer W for the second time for a minute, and the platen 2 chemical-mechanically polishes the third semiconductor wafer W for the first time for a minute. During this one minute, a fourth semiconductor wafer W is loaded onto the load-and-unload station 5. Then the carrier 13 picks up and holds the loaded fourth semiconductor wafer W.
Next, the carousel 9 rotates clockwise by 270 degrees. Consequently, as shown in FIG. 2E, the carrier 10 is returned to the load-and-unload station 5. Then the carrier 10 unloads the first semiconductor wafer W onto the load-and-unload station 5. The robot then stores this unloaded first semiconductor wafer W in a wafer cassette. At the same time, the platen 4 chemical-mechanically polishes the second semiconductor wafer W for the last time for a minute, the platen 3 chemical-mechanically polishes the third semiconductor wafer W for the second time for a minute, and the platen 2 chemical-mechanically polishes the fourth semiconductor wafer W for the first time for a minute. During this one minute, as shown in FIG. 2F, a fifth semiconductor wafer W is loaded onto the load-and-unload station 5. Then the carrier 10 picks up and holds the loaded fifth semiconductor wafer W.
After this, the above-described process is repeated. In this way, semiconductor wafers are sequentially polished.
In an operation mode of the CMP apparatus, called the batch mode, the platens 2, 3, and 4 polish the surfaces of semiconductor wafers W for the first time in parallel. An example of a manner in which the CMP apparatus operates in the batch mode is provided in the following. In this batch mode, each of the three semiconductor wafers is polished at exactly one platen, and is not polished separately at multiple platens as in the in-line mode.
First, as shown in FIG. 3A, the robot supplies a first semiconductor wafer W onto the load-and-unload station 5. Then the carrier 10 picks up and holds the loaded first semiconductor wafer W. Subsequently, the carousel 9 rotates counterclockwise by 90 degrees. Next, as shown in FIG. 3B, the robot supplies a second semiconductor wafer W onto the load-and-unload station 5. Then the carrier 11 picks up and holds the loaded second semiconductor wafer W. Subsequently, the carousel 9 rotates counterclockwise by 90 degrees. Next, as shown in FIG. 3C, the robot supplies a third semiconductor wafer W onto the load-and-unload station 5. Then the carrier 12 picks up and holds the loaded third semiconductor wafer W. Subsequently, the carousel 9 rotates counterclockwise by 90 degrees.
Consequently, as shown in FIG. 3D, the first semiconductor wafer W held by the carrier 10 is moved onto the platen 4, the second semiconductor wafer W held by the carrier 11 is moved onto the platen 3, and the third semiconductor wafer W held by the carrier 12 is moved onto the platen 2. Subsequently, the carriers 10, 11, and 12 descend onto the platens 4, 3, and 2, respectively. The first through third semiconductor wafers W are then chemical-mechanically polished for three minutes on the platens 4, 3, and 2, respectively. While the first through third semiconductor wafers W are being polished, the robot supplies a fourth semiconductor wafer W onto the load-and-unload station 5. Then the carrier 13 picks up and holds the loaded fourth semiconductor wafer W.
Next, the carousel 9 rotates clockwise by 90 degrees. Consequently, as shown in FIG. 3E, the third semiconductor wafer W held by the carrier 12 is moved onto the load-and-unload station 5. Then the robot unloads the third semiconductor wafer W into the wafer cassette. Next, the carousel 9 rotates clockwise by 90 degrees. Consequently, as shown in FIG. 3F, the second semiconductor wafer W held by the carrier 11 is moved onto the load-and-unload station 5. Then the robot unloads the second semiconductor wafer W into the wafer cassette. After this, the carousel 9 rotates clockwise by 90 degrees. Consequently, as shown in FIG. 4G, the first semiconductor wafer W held by the carrier 10 is moved onto the load-and-unload station 5. Then the robot unloads the first semiconductor wafer W into the wafer cassette.
Next, as shown in FIG. 4H, the robot supplies a fifth semiconductor wafer W onto the load-and-unload station 5. Then the carrier 10 picks up and holds the loaded fifth semiconductor wafer W. Subsequently, as shown in FIG. 4I, the carousel 9 rotates counterclockwise by 90 degrees. Then the robot supplies a sixth semiconductor wafer W onto the load-and-unload station 5, and the carrier 11 picks up and holds the loaded sixth semiconductor wafer W. After this, the carousel 9 rotates counterclockwise by 90 degrees. Subsequently, the fourth semiconductor wafer W held by the carrier 13, the fifth semiconductor wafer W held by the carrier 10, and the sixth semiconductor wafer W held by the carrier 11 are chemical-mechanically polished in parallel for three minutes on the platens 4, 3, and 2, respectively.
After this, the above-described process is repeated.
The performance of a CMP apparatus is evaluated based on such characteristics as the footprint and the throughput as well as the polish characteristic. Needless to say, the polish characteristic of a CMP apparatus needs to be excellent. However, characteristics such as the footprint and throughput of a CMP apparatus play important roles in evaluating the performance of a CMP apparatus. Both of these characteristics heavily influence the manufacturing cost of semiconductor wafers, and consequently the product cost of LSI. The footprint of a CMP apparatus represents the total area of the apparatus. In a clean room, it is desirable that a CMP apparatus occupy a small area. The throughput of a CMP apparatus represents the total number of semiconductor wafers the CMP apparatus can process per unit time. It is desirable that the throughput of a CMP apparatus be high.
In the above-explained in-line mode, while the three semiconductor wafers are being polished on three platens 2,3 and 4, the next semiconductor wafer is prepared by the remaining carrier. Thus, during the simultaneous dressing, in which the polish pad is dressed (conditioned) while the semiconductor wafer is being polished, the three carriers continue to polish the semiconductor wafers, except during the time interval in which the carousel 9 determines the rotation positions of the semiconductor wafers. Therefore, the carriers have a short non-polish time interval, or equivalently, a high operation rate, resulting in an excellent operation efficiency of the CMP apparatus. In the case in which the polish time interval is set to three minutes, and each of the platens 2 through 4 polishes a given semiconductor wafer for one minute (=60 [seconds]) by work-sharing, according to data shown on the 1996 VMIC (VLSI Multilevel Interconnection) Conference (Reference Number: Library of Congress No. 89-644090), the throughput of the above-described conventional CMP apparatus turns out to be 45 semiconductor wafers per hour in accordance with the following equation (1). In other words, the total number of semiconductor wafers the CMP apparatus can polish per hour is 45. Here, 20 [seconds] represents the length of time the carousel 9 spends in order to determine the rotation positions of the semiconductor wafers. EQU 3600/(60+20)=45 (1)
The above-described conventional CMP apparatus, which operates in the in-line mode, has a high throughput value. However, such polish characteristics as the polish stability and re-producibility of the above-described conventional CMP apparatus are unstable.
In a CMP process, it is very important that the throughput and polish performance or so-called process performance of a CMP apparatus be excellent and stable. For example, when 100 semiconductor wafers contained in a lot are chemical-mechanically polished, the polish characteristics of the CMP apparatus at the time the CMP apparatus polishes the tenth semiconductor wafer is required to be the same as that at the time the CMP apparatus polishes the 100th semiconductor wafer. The polish characteristics of the CMP apparatus heavily depend particularly on the performance of the polish pads. However, the material characteristics values of the polish pads, such as their thickness, elasticity recovery rates, and the like, differ minutely from one polish pad to another even if the polish pads have been manufactured under the same conditions. In addition, even if the polish pads of multiple platens are dressed under the same conditions, discrepancies among the polish characteristics of the polish pads gradually arise as the pad dressing is repeated.
Therefore, in order to polish many semiconductor wafers in a large number of lots, it is necessary to measure the thickness of the post-polish semiconductor wafers, for example, one semiconductor wafer for every 20 semiconductor wafers so as to reset the process parameters. In this way, the polish characteristics discrepancies among the polish pads are eliminated. In resetting the process parameters, the above-described conventional CMP apparatus, which operates in the in-line mode, polishes a semiconductor wafer using multiple polish pads. Hence, it is difficult to determine precisely which polish pads on the platens are problematic and how those problematic polish pads are affecting the process parameters. Therefore, in reality, it is difficult to operate the above-described conventional CMP apparatus in the in-line mode and have the conventional CMP apparatus perform the first split-operation polish.
On the other hand, in the above-explained batch mode, three platens simultaneously chemical-mechanically polish three semiconductor wafers. Each of the semiconductor wafers is processed on one platen to the end. Therefore, in the above-explained conventional CMP apparatus that operates in the batch mode, the above-described problem caused by the split-operation polish does not arise, and the polish characteristics of the CMP apparatus remain stable. However, after the first three semiconductor wafers have been polished simultaneously, fifth and sixth semiconductor wafers need to be newly supplied from the wafer cassette to the carriers. The fourth semiconductor wafer is picked up and held by the corresponding carrier while the three semiconductor wafers are being polished simultaneously.
It follows that the platens 2, 3, and 4 cannot polish the semiconductor wafers while the fifth and sixth semiconductor wafers are being introduced from the wafer cassette to the carriers. According to data shown on page 203 of the 1996 VMIC (VLSI Multilevel Interconnection) Conference (Reference Number: Library of Congress No. 89-644090), the required length of time during which the platens 2, 3, and 4 cannot polish the semiconductor wafers is in the range between 1.25 minutes (=75 seconds) and 1.75 minutes (=105 seconds). Hence, since the polish time interval is 3 minutes (=180 seconds), in accordance with the following equations (2) and (3), when the above-described conventional CMP apparatus operates in the batch mode, the throughput of the conventional CMP apparatus lies in the range between 37.9 semiconductor wafers per hour and 42.4 semiconductor wafers per hour. EQU {3600/(180+75)}.times.3=42.4 (2) EQU {3600/(180+105)}.times.3=37.9 (3)
Therefore, when the above-described conventional CMP apparatus operates in the batch mode, the CMP apparatus cannot achieve a high throughput value, such as 45 semiconductor wafers per hour that it achieves when it operates in the in-line mode.